| has gloss | eng: In integrated circuit design, dynamic logic (or sometimes clocked logic) is a design methodology logic family in digital logic that was popular in the 1970s and has seen a recent resurgence in the design of high speed digital electronics, particularly computer CPUs. Dynamic logic is distinguished from so-called static logic in that it uses a clock signal in its implementation of combinational logic circuits, that is, logic circuits in which the output is a function of only the current input. The usual use of a clock signal is to synchronize transitions in sequential logic circuits, and for most implementations of combinational logic, a clock signal is not even needed. To those unfamiliar with the challenges of digital logic design, then, it must seem a disadvantage that clocked logic relies so heavily on a clock signal. As will be shown in this article, however, there are certain circumstances in which dynamic logic has a clear advantage. |
